; filename ******** ADC.asm ************** 
; Lab 7  analog to digital convertor, 10-bit ADC
;    put your solution here
; commment

  absentry   ADC_Init
  absentry   ADC_In
  absentry   ADC_In2

EEPROM:       section  

;***********ADC routines*********************
ATD0CTL0  equ $0080  ; ATD Control Register 0
ATD0CTL1  equ $0081  ; ATD Control Register 1
ATD0CTL2  equ $0082  ; ATD Control Register 2
ATD0CTL3  equ $0083  ; ATD Control Register 3
ATD0CTL4  equ $0084  ; ATD Control Register 4
ATD0CTL5  equ $0085  ; ATD Control Register 5
ATD0DIEN  equ $008D  ; ATD Input Enable Mask Register
ATD0DR0   equ $0090  ; A/D Conversion Result Register 0
ATD0DR0L  equ $0091  ; A/D Conversion Result Register 0 (low byte)
ATD0DR1   equ $0092  ; A/D Conversion Result Register 1
ATD0DR2   equ $0094  ; A/D Conversion Result Register 2
ATD0DR3   equ $0096  ; A/D Conversion Result Register 3  
ATD0DR4   equ $0098  ; A/D Conversion Result Register 4
ATD0DR5   equ $009A  ; A/D Conversion Result Register 5
ATD0DR6   equ $009C  ; A/D Conversion Result Register 6
ATD0DR7   equ $009E  ; A/D Conversion Result Register 7
ATD0STAT0 equ $0086  ; A/D Status Register 0
ATD0STAT1 equ $008B  ; A/D Status Register 1
;            ATDDRxH                ATDCRxL   (9S12DP512)
; 8-bit left   MSB,6,5,4,3,2,1,LSB    U,U,z,z,z,z,z,z  (z means zero, U means unknown)
;10-bit left   MSB,8,7,6,5,4,3,2      1,LSB,z,z,z,z,z,z
; 8-bit right  z,z,z,z,z,z,z,z        MSB,6,5,4,3,2,1,LSB
;10-bit right  z,z,z,z,z,z,MSB,8      7,6,5,4,3,2,1,LSB
;        8-s-right  8-un-right 8-s-left 8-un-left 10-s-left 10-s-right 10-un-left 10-un-right
; 5.0 V    007F      00FF       7F00      FF00      7FC0      01FF       FFC0      03FF
; 2.5 V    0000      0080       0000      8000      0000      0000       8000      0200
; 0.0 V    FF80      0000       8000      0000      8000      FE00       0000      0000  

;****Initialize ADC*******
;one conversion, 2MHz clock, 10-bit mode
;Inputs: None
;Outputs: None
; assume 24 MHz E clock
; speed is 2(m+1)(s+n)/ fE = 2(5+1)(4+10)/24MHz = 7us
ADC_Init 
          movb  #$80,ATD0CTL2 ;power up
          movb  #$80,ATD0CTL3 ;1 sample
          movb  #$05,ATD0CTL4 ;10-bit 8-bit is $85
          rts
          

;*****Input sample from ADC*******
; perform 10-bit analog to digital conversion
;Inputs: RegD is channel number 0-7, e.g., $82 means channel 2
;Outputs: RegD is 10-bit ADC sample
; analog input    right justified(decimal)
;  0.00              0  (this Table is approximate)
;  0.02              4  (real data will be different)
;  0.04              8
;  1.25            256 
;  2.50            512
;  5.00           1023
; uses busy-wait synchronization
; bit 7 DJM Result Register Data Justification
;       1=right justified, 0=left justified
; bit 6 DSGN Result Register Data Signed or Unsigned Representation
;       1=signed, 0=unsigned
; bit 5 SCAN Continuous Conversion Sequence Mode
;       1=continuous, 0=single
; bit 4 MULT Multi-Channel Sample Mode
;       1=multiple channel, 0=single channel
; bit 3 0
; bit 2-0 CC,CB,CA channel number 0 to 7
ADC_In 
       staa ATD0CTL5 ; start ADC
loop   brclr ATD0STAT1,$01,loop
       ldd  ATD0DR0 ; 10-bit result
       rts

    
;*****Input sample from ADC channel 2*******
; perform 10-bit analog to digital conversion
;Inputs: none
;Outputs: RegD is 10-bit ADC sample
; analog input    right justified(decimal)
; analog input    right justified(decimal)
;  0.00              0  (this Table is approximate)
;  0.02              4  (real data will be different)
;  0.04              8
;  1.25            256 
;  2.50            512
;  5.00           1023
; uses busy-wait synchronization
; bit 7 DJM Result Register Data Justification
;       1=right justified, 0=left justified
; bit 6 DSGN Result Register Data Signed or Unsigned Representation
;       1=signed, 0=unsigned
; bit 5 SCAN Continuous Conversion Sequence Mode
;       1=continuous, 0=single
; bit 4 MULT Multi-Channel Sample Mode
;       1=multiple channel, 0=single channel
; bit 3 0
; bit 2-0 CC,CB,CA channel number 0 to 7
ADC_In2 
        ldaa  #$82 ; right justified channel 2
        jsr   ADC_In ; jump to general subroutine result in D
        rts
;* * * * * * * * End of ADC routines* * * * * * * * 

